From p. 4-59 of the Alpha AXP Architecture Manual:
	quiet NaN:	initial fraction bit of 1
	signaling NaN:	initial fraction bit of 0
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From p. 21 of SPARC Architecture Manual v8:
[same choice as Alpha]
	quiet NaN:	initial fraction bit of 1
	signaling NaN:	initial fraction bit of 0
------------------------------------------------------------------------
From p. 145 of The PowerPC Architecture:
[same as Alpha and SPARC]
	quiet NaN:	initial fraction bit of 1
	signaling NaN:	initial fraction bit of 0
------------------------------------------------------------------------
From p. 2-5 of i860 Microprocessor Programmer's Reference Manual:
[same as Alpha, SPARC, PowerPC]
	quiet NaN:	initial fraction bit of 1
	signaling NaN:	initial fraction bit of 0
------------------------------------------------------------------------
From p. 2-15 of MC68881 Floating-Point Coprocessor Users Manual:
[same as Alpha, SPARC, PowerPC, Intel i860]
	quiet NaN:	initial fraction bit of 1
	signaling NaN:	initial fraction bit of 0
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From p. 5-3 (sequential 87 of 216) Intel IA-64 Architecture Software
Developer's Manual, Rev 1.0:
[same as Alpha, SPARC, PowerPC, Intel i860, MC68881]
	quiet NaN:	initial fraction bit of 1
	signaling NaN:	initial fraction bit of 0
------------------------------------------------------------------------
From p. 8-7 of Hewlett-Packard PA-RISC 2.0 Architecture:
[opposite of Alpha, SPARC, PowerPC, i860]
	quiet NaN:	initial fraction bit of 0
	signaling NaN:	initial fraction bit of 1
------------------------------------------------------------------------
From p. E-2 of MIPS RISC Architecture:
[no distinction between NaNs]
	NaN:		initial fraction bit of 0

Thu Dec 5 17:48:11 2002: Correction following discussions with an SGI
engineering staff member, checking with more recent MIPS assembler
manuals, and numerical experiments in hoc: both types are NaN are
supported, with encoding like on Sun SPARC, on at least MIPS R4000,
R5000, and R8000 processors.
[like HP PA-RISC, opposite of Alpha, SPARC, PowerPC, i860]
	quiet NaN:	initial fraction bit of 0
	signaling NaN:	initial fraction bit of 1
------------------------------------------------------------------------
From Palmer and Morse The 8087 Primer and p. I-25 of iAPX 286
Programmer's Reference Manual:
[no distinction between NaNs]
	NaN:		at least one nonzero fraction bit
Generated NaNs have negative sign bit.

Experiments on Pentium III show 0/0 -> 0xfff80000_00000000, so the
leading fraction bit is the only nonzero generated.  However, this can
be explicitly negated to obtain 0x7ff80000_00000000.
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