%%% -*-BibTeX-*- %%% ==================================================================== %%% BibTeX-file{ %%% author = "Nelson H. F. Beebe", %%% version = "1.10", %%% date = "06 June 2003", %%% time = "05:10:32 MDT", %%% filename = "microchip.bib", %%% address = "Center for Scientific Computing %%% University of Utah %%% Department of Mathematics, 110 LCB %%% 155 S 1400 E RM 233 %%% Salt Lake City, UT 84112-0090 %%% USA", %%% telephone = "+1 801 581 5254", %%% FAX = "+1 801 581 4148", %%% URL = "http://www.math.utah.edu/~beebe", %%% checksum = "37395 5811 24451 238961", %%% email = "beebe at math.utah.edu, beebe at acm.org, %%% beebe at computer.org, beebe at ieee.org %%% (Internet)", %%% codetable = "ISO/ASCII", %%% keywords = "bibliography; BibTeX; microprocessors", %%% supported = "yes", %%% docstring = "This is a selected bibliography of %%% publications about current microprocessors %%% possibly suitable for desktop and cluster %%% computing. Preference is given to book %%% references, rather than research articles, %%% unless the architecture is so new that book %%% coverage is limited or unavailable. %%% %%% At version 1.10, the year coverage looked %%% like this: %%% %%% 1985 ( 2) 1992 ( 19) 1999 ( 22) %%% 1986 ( 0) 1993 ( 8) 2000 ( 36) %%% 1987 ( 3) 1994 ( 30) 2001 ( 5) %%% 1988 ( 9) 1995 ( 17) 2002 ( 2) %%% 1989 ( 13) 1996 ( 18) 2003 ( 2) %%% 1990 ( 24) 1997 ( 24) %%% 1991 ( 16) 1998 ( 14) %%% %%% Article: 77 %%% Book: 128 %%% InProceedings: 7 %%% Manual: 12 %%% MastersThesis: 1 %%% Misc: 6 %%% Proceedings: 16 %%% TechReport: 17 %%% %%% Total entries: 264 %%% %%% The checksum field above contains a CRC-16 %%% checksum as the first value, followed by the %%% equivalent of the standard UNIX wc (word %%% count) utility output of lines, words, and %%% characters. This is produced by Robert %%% Solovay's checksum utility.", %%% } %%% ==================================================================== @Preamble{"\input bibnames.sty " # "\input path.sty " # "\hyphenation{ }" } %%% ==================================================================== %%% Acknowledgement abbreviations: @String{ack-nhfb = "Nelson H. F. Beebe, Center for Scientific Computing, University of Utah, Department of Mathematics, 110 LCB, 155 S 1400 E RM 233, Salt Lake City, UT 84112-0090, USA, Tel: +1 801 581 5254, FAX: +1 801 581 4148, e-mail: \path|beebe@math.utah.edu|, \path|beebe@acm.org|, \path|beebe@computer.org|, \path|beebe@ieee.org| (Internet), URL: \path|http://www.math.utah.edu/~beebe/|"} %%% ==================================================================== %%% Journal abbreviations: @String{j-BYTE = "Byte Magazine"} @String{j-CACM = "Communications of the ACM"} @String{j-COMP-ARCH-NEWS = "ACM SIGARCH Computer Architecture News"} @String{j-COMPUTER = "Computer"} @String{j-DDJ = "Dr. Dobb's Journal of Software Tools"} @String{j-HEWLETT-PACKARD-J = "Hew\-lett-Pack\-ard Journal: technical information from the laboratories of Hew\-lett-Pack\-ard Company"} @String{j-IBM-JRD = "IBM Journal of Research and Development"} @String{j-IEEE-CGA = "IEEE Computer Graphics and Applications"} @String{j-IEEE-CONCURR = "IEEE Concurrency"} @String{j-IEEE-MICRO = "IEEE Micro"} @String{j-INT-J-HIGH-SPEED-COMPUTING = "International Journal of High Speed Computing"} @String{j-LECT-NOTES-COMP-SCI = "Lecture Notes in Computer Science"} @String{j-LINUX-J = "Linux Journal"} @String{j-MICROPROC-MICROSYS = "Microprocessors and Microsystems"} @String{j-SIGPLAN = "ACM SIG{\-}PLAN Notices"} %%% ==================================================================== %%% Publishers and their addresses: @String{pub-ACM = "ACM Press"} @String{pub-ACM:adr = "New York, NY 10036, USA"} @String{pub-AMD = "Advanced Micro Devices, Inc."} @String{pub-AMD:adr = "One AMD Place, P.O. Box 3453, Sunnyvale, California, USA"} @String{pub-AP-PROFESSIONAL = "AP Professional"} @String{pub-AP-PROFESSIONAL:adr = "Boston, MA, USA"} @String{pub-AW = "Ad{\-d}i{\-s}on-Wes{\-l}ey"} @String{pub-AW:adr = "Reading, MA, USA"} @String{pub-AW-LONGMAN = "Ad{\-d}i{\-s}on-Wes{\-l}ey Longman"} @String{pub-AW-LONGMAN:adr = "Harlow, Essex CM20 2JE, England"} @String{pub-AWDP = "Ad{\-d}i{\-s}on-Wes{\-l}ey Developers Press"} @String{pub-AWDP:adr = "Reading, MA, USA"} @String{pub-BUTTERWORTH-HEINEMANN = "Butterworth-Heinemann"} @String{pub-BUTTERWORTH-HEINEMANN:adr = "Boston, MA, USA"} @String{pub-CRC = "CRC Press"} @String{pub-CRC:adr = "2000 N.W. Corporate Blvd., Boca Raton, FL 33431-9868, USA"} @String{pub-DP = "Digital Press"} @String{pub-DP:adr = "12 Crosby Drive, Bedford, MA 01730, USA"} @String{pub-HP = "Hewlett-Packard Corporation"} @String{pub-HP:adr = "Rockville, MD 20850, USA"} @String{pub-IBM = "IBM Corporation"} @String{pub-IBM:adr = "San Jose, CA, USA"} @String{pub-IBM-REDBOOKS = "IBM Redbooks"} @String{pub-IBM-REDBOOKS:adr = "11400 Burnet Road, Austin, TX 78758-3493, USA"} @String{pub-IEEE = "IEEE Computer Society Press"} @String{pub-IEEE:adr = "1109 Spring Street, Suite 300, Silver Spring, MD 20910, USA"} @String{pub-INTEL = "Intel Corporation"} @String{pub-INTEL:adr = "Santa Clara, CA, USA"} @String{pub-IOS = "IOS Press"} @String{pub-IOS:adr = "Amsterdam, The Netherlands"} @String{pub-KLUWER = "Kluwer Academic Publishers"} @String{pub-KLUWER:adr = "Dordrecht, The Netherlands"} @String{pub-MACMILLAN = "Macmillan Publishing Co., Inc."} @String{pub-MACMILLAN:adr = "New York, NY, USA"} @String{pub-MCGRAW-HILL = "Mc{\-}Graw-Hill"} @String{pub-MCGRAW-HILL:adr = "New York, NY, USA"} @String{pub-MORGAN-KAUFMANN = "Morgan Kaufmann Publishers"} @String{pub-MORGAN-KAUFMANN:adr = "Los Altos, CA 94022, USA"} @String{pub-MORGAN-KAUFMANN:adrnew = "2929 Campus Drive, Suite 260, San Mateo, CA 94403, USA"} @String{pub-MOTOROLA = "Motorola Corporation"} @String{pub-MOTOROLA:adr = "Phoenix, AZ, USA"} @String{pub-MT = "M\&T Books"} @String{pub-MT:adr = "M\&T Publishing, Inc., 501 Galveston Drive, Redwood City, CA 94063, USA"} @String{pub-OHMSHA = "Ohmsha, Ltd."} @String{pub-OHMSHA:adr = "3-1 Kanda Nishiki-cho, Chiyoda-ku, Tokyo 101, Japan"} @String{pub-ORA = "O'Reilly \& {Associates, Inc.}"} @String{pub-ORA:adr = "981 Chestnut Street, Newton, MA 02164, USA"} @String{pub-OXFORD = "Oxford University Press"} @String{pub-OXFORD:adr = "Walton Street, Oxford OX2 6DP, UK"} @String{pub-PEREGRINUS = "Peter Peregrinus Ltd"} @String{pub-PEREGRINUS:adr = "Michael Faraday House, Six Hills Way, Stevenage, Herts SG1 2AY, UK"} @String{pub-PH = "Pren{\-}tice-Hall"} @String{pub-PH:adr = "Upper Saddle River, NJ 07458, USA"} @String{pub-PHI = "Pren{\-}tice-Hall International"} @String{pub-PHI:adr = "Englewood Cliffs, NJ 07632, USA"} @String{pub-PHPTR = "Pren{\-}tice-Hall PTR"} @String{pub-PHPTR:adr = "Upper Saddle River, NJ 07458, USA"} @String{pub-PITMAN = "Pitman Publishing Ltd."} @String{pub-PITMAN:adr = "London, UK"} @String{pub-QUE = "Que Corporation"} @String{pub-QUE:adr = "Indianapolis, IN, USA"} @String{pub-SAMS = "Howard W. Sams"} @String{pub-SAMS:adr = "Indianapolis, IN 46268, USA"} @String{pub-SAUNDERS = "Saunders College Pub."} @String{pub-SAUNDERS:adr = "Fort Worth, TX, USA"} @String{pub-SIEMENS = "Siemens Aktiengesellschaft"} @String{pub-SIEMENS:adr = "Berlin and Munich, Germany"} @String{pub-SUN = "Sun Microsystems"} @String{pub-SUN:adr = "901 San Antonio Road, Palo Alto, CA 94303-4900, USA"} @String{pub-SV = "Spring{\-}er-Ver{\-}lag"} @String{pub-SV:adr = "Berlin, Germany~/ Heidelberg, Germany~/ London, UK~/ etc."} @String{pub-TELOS = "TELOS division of Springer-Verlag"} @String{pub-TELOS:adr = "Santa Clara, CA, USA and New York, NY, USA"} @String{pub-UNIV-VIDEO-COMM = "University Video Communications"} @String{pub-UNIV-VIDEO-COMM:adr = "Stanford, CA, USA"} @String{pub-VNR = "Van Nostrand Reinhold Co."} @String{pub-VNR:adr = "New York, NY, USA"} @String{pub-WILEY-INTERSCIENCE = "Wiley-In{\-}ter{\-}sci{\-}ence"} @String{pub-WILEY-INTERSCIENCE:adr = "New York, NY, USA"} @String{pub-WINDCREST = "Windcrest/McGraw-Hill"} @String{pub-WINDCREST:adr = "Blue Ridge Summit, PA, USA"} %%% ==================================================================== %%% Bibliography entries, sorted by citation key. @Article{Ahi:1992:DVH, author = "Ali M. Ahi and Gregory D. Burroughs and Audrey B. Gore and Steve W. LaMar and Chi-Yen R. Lin and A. L. Wiemann", title = "Design verification of the {HP 9000 Series 700 PA-RISC} workstations", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "4", pages = "34--42", month = aug, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Tue Mar 25 14:12:15 MST 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", abstract = "First a high-level system model was simulated and compared with a reference machine running both HP standard and pseudorandom test programs. Then the same tests were run on hardware prototypes. All chips were able to boot the operating system on first silicon.", acknowledgement = ack-nhfb, affiliation = "Hewlett Packard Co., Palo Alto, CA, USA", classcodes = "C5430 (Microcomputers); C5470 (Performance evaluation and testing)", classification = "C5430 (Microcomputers); C5470 (Performance evaluation and testing)", corpsource = "Hewlett Packard Co., Palo Alto, CA, USA", keywords = "computer testing; computers; formal verification; Hardware prototypes; hardware prototypes; Hewlett Packard; high-level system; High-level system model; HP 9000 Series 700 PA-RISC workstations; model; Operating system; operating system; Pseudorandom test programs; pseudorandom test programs; reduced instruction set computing; Reference machine; reference machine; workstations", thesaurus = "Computer testing; Formal verification; Hewlett Packard computers; Reduced instruction set computing; Workstations", treatment = "P Practical", xxnote = "Check authors??", } @Manual{AMD:2000:AKE, title = "{AMD-K62-E+} Embedded Processor Data Sheet", organization = pub-AMD, address = pub-AMD:adr, pages = "xxii + 346", month = sep, year = "2000", bibdate = "Tue Jan 16 16:55:41 2001", note = "Order number 23542A/0", URL = "http://www.amd.com/products/epd/processors/6.32bitproc/8.amdk6fami/28.amdk62e/23542/23542a.pdf", acknowledgement = ack-nhfb, } @Manual{AMD:2000:TM, title = "{3DNow!} Technology Manual", organization = pub-AMD, address = pub-AMD:adr, pages = "x + 62", month = mar, year = "2000", bibdate = "Tue Jan 16 16:55:41 2001", note = "Order number 21928G/0.", URL = "http://www.amd.com/products/epd/processors/6.32bitproc/8.amdk6fami/26.amdk62e/21928/21928.pdf", acknowledgement = ack-nhfb, } @Book{Anderson:1995:PPS, author = "Don Anderson and Tom Shanley", title = "{Pentium} processor system architecture", publisher = pub-AW, address = pub-AW:adr, edition = "Second", pages = "xxvii + 433", year = "1995", ISBN = "0-201-40992-5", LCCN = "QA76.8.P46 A63 1995", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", series = "PC system architecture series", acknowledgement = ack-nhfb, keywords = "Pentium (microprocessor)", } @Article{Anonymous:1992:HSP, author = "Anonymous", title = "{HP} Standard {PA-RISC} Test Programs", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "4", pages = "35--??", month = aug, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Sun May 26 09:44:33 MDT 1996", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", acknowledgement = ack-nhfb, } @Article{Anonymous:1992:PPM, author = "Anonymous", title = "{PA-RISC} Performance Modeling and Simulation", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "4", pages = "21--??", month = aug, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Sun May 26 09:44:33 MDT 1996", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", acknowledgement = ack-nhfb, } @Article{Anonymous:1997:OI, author = "Anonymous", title = "Optimizing the {IA-64}", journal = j-IEEE-MICRO, volume = "17", number = "5", pages = "6--6", month = "????", year = "1997", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Science Citation Index database (1980--2000); ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", acknowledgement = ack-nhfb, } @Book{Antonakos:1997:PM, author = "James L. Antonakos", title = "The Pentium microprocessor", publisher = pub-PH, address = pub-PH:adr, pages = "xv + 539", year = "1997", ISBN = "0-02-303614-1", LCCN = "QA76.8.P46 A64 1997", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Includes index.", acknowledgement = ack-nhfb, keywords = "Pentium (microprocessor)", } @Book{Apple:1994:IMPa, author = "{Apple Computer, Inc}", title = "Inside {Macintosh}. {PowerPC} Numerics", publisher = pub-AW, address = pub-AW:adr, pages = "various", year = "1994", ISBN = "0-201-40728-0", LCCN = "QA76.8.M3 I5622 1994", bibdate = "Fri Jan 5 07:23:44 MST 2001", bibsource = "University of California MELVYL catalog", price = "US\$28.95, CDN\$37.95", series = "Apple technical library", acknowledgement = ack-nhfb, keywords = "Macintosh (computer); PowerPC microprocessors", } @Book{Apple:1994:IMPb, author = "{Apple Computer, Inc}", title = "Inside {Macintosh}. {PowerPC} system software", publisher = pub-AW, address = pub-AW:adr, pages = "various", year = "1994", ISBN = "0-201-40727-2", LCCN = "QA76.8.M3 I528 1994", bibdate = "Fri Jan 5 07:23:44 MST 2001", bibsource = "University of California MELVYL catalog", price = "US\$24.95, CDN\$31.95", series = "Apple technical library", acknowledgement = ack-nhfb, keywords = "Macintosh (computer); PowerPC microprocessors; systems software", } @Book{Apple:1995:PMC, author = "{Apple Computer, Inc.} and {IBM Corporation} and {Motorola, Inc.}", title = "{PowerPC} Microprocessor Common Hardware Reference Platform: {A} System Architecture", publisher = pub-MORGAN-KAUFMANN, address = pub-MORGAN-KAUFMANN:adr, pages = "xxiv + 309", year = "1995", ISBN = "1-55860-394-8", LCCN = "QA76.89.P67P74 1995", bibdate = "Fri Jan 19 08:14:50 1996", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", price = "US\$39.95", acknowledgement = ack-nhfb, } @Article{Asprey:1993:PFP, author = "T. Asprey and G. S. Averill and E. DeLano and R. Mason and B. Weiner and J. Yetter", title = "Performance Features of the {PA7100} Microprocessor", journal = j-IEEE-MICRO, volume = "13", number = "3", pages = "22--35", month = jun, year = "1993", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib; Science Citation Index database (1980--2000)", acknowledgement = ack-nhfb, classcodes = "C5220 (Computer architecture)", corpsource = "Hewlett-Packard, Fort Collins, CO, USA", keywords = "cache design; computer; floating-point unit; interface bus; microprocessor chips; microprocessor instruction execution; PA-RISC; PA7100 CPU; pipeline; precision-architecture; reduced instruction set computing; reduced-instruction-set-; system; translation look-aside buffer; verification; virtual address translation", treatment = "P Practical", } @Article{Atkins:1991:PIM, author = "Mark Atkins", title = "Performance and the {i860} Microprocessor", journal = j-IEEE-MICRO, volume = "11", number = "5", pages = "24--27, 72--78", month = oct, year = "1991", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Science Citation Index database (1980--2000); Compendex database; ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", abstract = "Pipelining, parallelism, and internal caches help this million-transistor chip enhance performance", acknowledgement = ack-nhfb, affiliation = "Intel Corp, Santa Clara, CA, USA", classcodes = "B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5220 (Computer architecture); C5470 (Performance evaluation and testing)", classification = "714.2; 721.3; 722.4", corpsource = "Intel Corp., Santa Clara, CA, USA", keywords = "Cache memory; caches; Computer architecture; digital signal; Explicit pipelines; Floating-point pipelines; graphics; high-bandwidth registers; I860 cpu; i860 CPU; I860 microprocessor; instruction set computing; instructions; Intel microprocessor; memory-performance optimizations; microprocessor; Microprocessor chips; microprocessor chips; Parallel processing systems; parallelism; performance evaluation; Pipeline processing systems; pipelining; processing; reduced; RISC; simultaneous floating-point operations; Six-stage pipelines; two-instruction-per-clock mode", treatment = "P Practical", } @Book{ATT:1990:SVA, author = "{American Telephone and Telegraph Company}", title = "{System V} application binary interface: {SPARC} processor supplement", publisher = pub-PH, address = pub-PH:adr, pages = "various", year = "1990", ISBN = "0-13-877630-X", LCCN = "QA76.76.O63 S9745 1990 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "UNIX System V (computer file)", } @Book{ATT:1991:SVA, author = "{American Telephone and Telegragh Company}", title = "{System V} application binary interface: {MIPS} processor supplement: {UNIX System V}", publisher = pub-PH, address = pub-PH:adr, pages = "various", year = "1991", ISBN = "0-13-880170-3", LCCN = "QA76.76.O63 S9742 1991 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "UNIX System V (computer file); MIPS-x (microprocessor)", } @Article{Averill:1999:CIM, author = "R. M. {Averill III} and K. G. Barkley and M. A. Bowen and P. J. Camporese and A. H. Dansky and R. F. Hatch and D. E. Hoffman and M. D. Mayo and S. A. McCabe and T. G. McNamara and T. J. McPherson and G. A. Northrop and L. Sigal and H. H. Smith and D. A. Webber and P. M. Williams", title = "Chip integration methodology for the {IBM S/390 G5} and {G6} custom microprocessors", journal = j-IBM-JRD, volume = "43", number = "5/6", pages = "681--706", month = "????", year = "1999", CODEN = "IBMJAE", ISSN = "0018-8646", bibdate = "Wed Apr 19 18:58:23 MDT 2000", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ibmjrd.bib", URL = "http://www.research.ibm.com/journal/rd/435/averill.html", acknowledgement = ack-nhfb, } @Article{Bakoglu:1990:IRS, author = "H. B. Bakoglu and G. F. Grohoski and R. K. Montoye", title = "The {IBM RISC System}\slash 6000 processor: Hardware overview", journal = j-IBM-JRD, volume = "34", number = "1", pages = "12--22", month = jan, year = "1990", CODEN = "IBMJAE", ISSN = "0018-8646", bibdate = "Tue Mar 25 14:26:59 MST 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ibmjrd.bib", abstract = "A highly concurrent superscalar second-generation family of RISC workstations and servers is described. The RISC System\slash 6000 family is based on the new IBM POWER (performance optimization with enhanced RISC) architecture; the hardware implementation takes advantage of this powerful RISC architecture and employs sophisticated design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio. The RS\slash 6000 CPU features multiple-instruction dispatch, multiple functional units that operate concurrently, separate instruction and data caches, and zero-cycle branches. In this superscalar implementation, at a given cycle the equivalent of five operations can be executed simultaneously (a branch, a condition-register operation, and a floating-point multiply-add). The RS\slash 6000 family supports the IBM Micro Channel architecture as well as high-speed serial optical links to provide a high-bandwidth I/O subsystem.", acknowledgement = ack-nhfb, affiliation = "IBM Adv. Workstations Div., Austin, TX, USA", classcodes = "C5440 (Multiprocessor systems and techniques); C5220 (Computer architecture)", classification = "C5220 (Computer architecture); C5440 (Multiprocessor systems and techniques)", corpsource = "IBM Adv. Workstations Div., Austin, TX, USA", keywords = "architecture; branch; Branch; caches; concurrent superscalar second-generation family; Concurrent superscalar second-generation family; condition-register; Condition-register operation; CPI ratio; Cycle time; cycle time; cycles-per-instruction; Cycles-per-instruction ratio; data; Data caches; floating-point multiply-add; Floating-point multiply-add; high-bandwidth I/O; High-bandwidth I/O subsystem; High-bandwidth I/O subsystem, RISC servers; IBM computers; IBM Micro Channel; IBM Micro Channel architecture; IBM POWER architecture; IBM RISC System/6000; IBM RISC System/6000 processor; IBM RISC System\slash 6000 processor; instruction caches; Instruction caches; instruction dispatch; Multiple functional units; multiple functional units; multiple-; Multiple-instruction dispatch; multiprocessing systems; operation; performance optimization with enhanced; Performance optimization with enhanced RISC; processor; ratio; reduced instruction; RISC; RISC architecture; RISC servers; RISC workstations; RS/6000 CPU; RS\slash 6000 CPU; serial optical links; Serial optical links; set computing; subsystem; zero-cycle branches; Zero-cycle branches", thesaurus = "IBM computers; Multiprocessing systems; Reduced instruction set computing", treatment = "P Practical", } @Book{Bhandarkar:1996:AIA, author = "Dileep P. Bhandarkar", title = "{Alpha} implementations and architecture: complete reference and guide", publisher = pub-DP, address = pub-DP:adr, pages = "xviii + 328", year = "1996", ISBN = "1-55558-130-7", LCCN = "QA76.8.A176B47 1996", bibdate = "Thu Aug 07 13:42:54 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", price = "US\$41.95", acknowledgement = ack-nhfb, } @Article{Bharadwaj:2000:IIC, author = "Jay Bharadwaj and William Y. Chen and Weihaw Chuang and Gerolf Hoflehner and Kishore Menezes and Kalyan Muthukumar and Jim Pierce", title = "The {Intel IA-64} Compiler Code Generator", journal = j-IEEE-MICRO, volume = "20", number = "5", pages = "44--53", month = sep # "\slash " # oct, year = "2000", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Tue Oct 10 06:00:40 MDT 2000", bibsource = "http://www.computer.org/micro/mi2000/; ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", URL = "http://www.computer.org/micro/mi2000/m5044abs.htm ; http://dlib.computer.org/mi/books/mi2000/pdf/m5044.pdf", acknowledgement = ack-nhfb, } @Article{Birman:1990:DWS, author = "Mark Birman and Allen Samuels and George Chu and Ting Chuk and Larry Hu and John McLeod and John Barnes", title = "Developing the {WTL3170\slash 3171 Sparc} Floating-Point Coprocessors", journal = j-IEEE-MICRO, volume = "10", number = "1", pages = "55--64", month = feb, year = "1990", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Compendex database; garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt; Science Citation Index database (1980--2000); ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", abstract = "Contending with dual floating-point interfaces at both 25 and 40 MHz posed an extraordinary challenge in coprocessor development.", acknowledgement = ack-nj # " and " # ack-nhfb, affiliation = "Weitek Corp, Sunnyvale, CA, USA", classcodes = "B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5230 (Digital arithmetic methods)", classification = "721; 722; 723", conference = "First Annual Hot Chips Symposium", corpsource = "Weitek Corp., Sunnyvale, CA, USA", keywords = "64-b ALU; bus organization; Circuits; Computer Architecture; Computer Interfaces; Computers, Microcomputer; digital arithmetic; divide/square-root; Divide/Square-Root Unit; floating-point; Floating-Point Adder; floating-point controller functions; Floating-Point Multiplier; integer; microprocessor chips; multiplier; register files; Sparc Floating-Point Coprocessors; system behavioral-level modeling; unit; units; WTL3170/3171 Sparc floating-point coprocessors", meetingabr = "First Annu Hot Chips Symp", meetingaddress = "Palo Alto, CA, USA", meetingdate = "Jun 26--27 1989", meetingdate2 = "06/26--27/89", sponsor = "IEEE Computer Soc, Palo Alto, CA, USA", treatment = "P Practical", } @Article{Bishop:1996:PAA, author = "J. W. Bishop and M. J. Campion and T. L. Jeremiah and S. J. Mercier and E. J. Mohring and K. P. Pfarr and B. G. Rudolph and G. S. Still and T. S. White", title = "{PowerPC AS A10} 64-bit {RISC} microprocessor", journal = j-IBM-JRD, volume = "40", number = "4", pages = "495--505", month = "????", year = "1996", CODEN = "IBMJAE", ISSN = "0018-8646", bibdate = "Fri Sep 20 13:33:11 1996", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ibmjrd.bib", URL = "http://www.almaden.ibm.com/journal/rd40-4.html#10", abstract = "The PowerPC AS* A10 64-bit RISC microprocessor is a 4.7-million-transistor integrated circuit design, using IBM CMOS 5L 0.5-$\mu$m, 3-V, four-level-metal ASIC technology. Support for the PowerPC AS architecture is implemented in a 213-mm$^2$ die using a semicustom design methodology. Chip density and speed are enhanced through the use of custom macros and multiport arrays. An on-chip phase-locked-loop circuit is used to reduce chip-to-chip clock skew. Full utilization of the four-level-metal interconnect technology was achieved through architectural floorplanning, performance clustering, and timing-driven placement and wiring, with a total wire length of over 102 meters placed on the 14.6 $\times$ 14.6-mm die. The microprocessor is a pipelined, superscalar design with five separate functional units, a 4KB instruction cache, and an 8KB data cache. The design includes parity, error-correction, and error-logging functions, as well as self-test for logic and arrays during power-on. The design is robust and implements a wide range of performance configurations at the system level, allowing direct attachment of DRAM to the processor, or high-performance L2 cache options using high-speed SRAM. An on-chip system I/O bus and bus controller are provided for attachment of peripherals.", acknowledgement = ack-nhfb, xxlibnote = "Issue missing from UofUtah Marriott Library", } @Book{Blaauw:1997:CAC, author = "Gerrit A. Blaauw and Frederick P. {Brooks, Jr.}", title = "Computer architecture: concepts and evolution", publisher = pub-AW, address = pub-AW:adr, pages = "xlviii + 1213", year = "1997", ISBN = "0-201-10557-8", LCCN = "QA76.9.A73 B57 1997", bibdate = "Wed Jul 09 17:22:33 1997", price = "US\$59.95", acknowledgement = ack-nhfb, bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @Article{Blinn:1997:JBCa, author = "James F. Blinn", title = "{Jim Blinn}'s Corner: Fugue for MMX", journal = j-IEEE-CGA, volume = "17", number = "2", pages = "88--93", month = mar # "\slash " # apr, year = "1997", note = "Makes several cogent comments about deficiencies in the Intel MMX pixel-processing instruction set \cite{Peleg:1997:IMM} for use in image compositing.", acknowledgement = ack-nhfb, CODEN = "ICGADZ", ISSN = "0272-1716", bibdate = "Mon Mar 03 09:18:04 1997", } @Article{Bockhaus:1997:EVH, author = "J. W. Bockhaus and R. Bhatia and C. M. Ramsey and J. R. Butler and D. J. Ljung", title = "Electrical Verification of the {HP PA 8000} Processor", journal = j-HEWLETT-PACKARD-J, volume = "48", number = "4", pages = "32--39", month = aug, year = "1997", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Wed Mar 25 15:17:10 MST 1998", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", URL = "http://www.hp.com/hpj/97aug/au97a4.htm", abstract = "Electrical verification applies techniques from both functional verification and reliability and environmental testing to improve the quality of the CPU. Electrical verification checks that the CPU functions correctly under stressful environmental conditions, well outside the normal operating environment.", acknowledgement = ack-nhfb, classification = "B0170E (Production facilities and engineering)C5130 (Microprocessor chips); B0170N (Reliability); B1265F (Microprocessors and microcomputers); C5470 (Performance evaluation and testing)", keywords = "computer testing; electrical verification; environmental testing; functional verification; Hewlett Packard computers; HP PA 8000 processor; microprocessor chips; normal operating environment; reliability; stressful environmental conditions", treatment = "A Application; P Practical", } @Article{Bollinger:1992:PHK, author = "D. E. Bollinger and F. P. Lemmon and D. L. Yamine", title = "Providing {HP-UX} kernel functionality on a new {PA-RISC} architecture", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "3", pages = "11--14", month = jun, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Tue Mar 25 14:12:15 MST 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", abstract = "The aggressive schedule for the development of the HP 9000 Series 700 systems required the development team in the HP-UX kernel laboratory to consider some modifications to the normal software development process, the number of product features, and the management structure. The goals for the product features were to change or add the minimum number of HP-UX kernel functions that would ensure customer satisfaction, meet performance goals, and adapt to a new I/O system. This version of the HP-UX kernel code became known as minimum core functionality, or MCF.", acknowledgement = ack-nhfb, affiliation = "Hewlett-Packard Co., Palo Alto., CA, USA", classcodes = "C0310F (Software development management); C6110B (Software engineering techniques); C6150J (Operating systems)", classification = "C0310F (Software development management); C6110B (Software engineering techniques); C6150J (Operating systems)", corpsource = "Hewlett-Packard Co., Palo Alto., CA, USA", keywords = "(computers); development process; Development team; development team; DP management; engineering; functionality; Hewlett Packard computers; HP 9000 Series 700 systems; HP-UX 8.0; HP-UX kernel functionality; Management structure; management structure; minimum core; Minimum core functionality; operating systems; PA-RISC architecture; reduced instruction set computing; software; Software development process", thesaurus = "DP management; Hewlett Packard computers; Operating systems [computers]; Reduced instruction set computing; Software engineering", treatment = "P Practical", } @Book{Brey:1995:IMP, author = "Barry B. Brey", title = "The {Intel} 32-bit microprocessors: 80386, 80486, and {Pentium} microprocessors", publisher = pub-PH, address = pub-PH:adr, pages = "xii + 801", year = "1995", ISBN = "0-02-314260-X", LCCN = "QA 76.8 I2684 B74 1995", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Intel 80386 (microprocessor); Intel 80486 (microprocessor); Pentium (microprocessor)", } @Book{Brey:1996:PPP, author = "Barry B. Brey", title = "Programming the 80286, 80386, 80486, and {Pentium}-based personal computer", publisher = pub-PH, address = pub-PH:adr, pages = "x + 786", year = "1996", ISBN = "0-02-314263-4", LCCN = "QA76.8.I2674 B77 1996", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Intel 80xxx series microprocessors --- programming; Pentium (microprocessor) --- programming", } @Book{Brey:1997:IMP, author = "Barry B. Brey", title = "The {Intel} microprocessors: 8086\slash 8088, 80186\slash 80188, 80286, 80386, 80486, {Pentium}, and {Pentium Pro} processor", publisher = pub-PH, address = pub-PH:adr, edition = "Fourth", pages = "xv + 907", year = "1997", ISBN = "0-13-260670-4", LCCN = "QA76.8.I2674 B75 1997", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Intel 80xxx series microprocessors; Pentium (microprocessor)", } @Book{Brey:2000:IMP, author = "Barry B. Brey", title = "The {Intel} microprocessors: 8086\slash 8088, 80186\slash 80188, 80286, 80386, 80486, {Pentium}, {Pentium Pro}, and {Pentium II} processors: architecture, programming, and interfacing", publisher = pub-PH, address = pub-PH:adr, edition = "Fifth", pages = "ix + 966", year = "2000", ISBN = "0-13-995408-2", LCCN = "QA76.8.I2674 B76 2000", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Intel 80xxx series microprocessors; Pentium (microprocessor)", } @Book{Brookes:1989:IOT, author = "Graham R. Brookes and Andrew J. Stewart", title = "Introduction to occam 2 on the transputer", publisher = pub-MACMILLAN, address = pub-MACMILLAN:adr, pages = "vii + 102", year = "1989", ISBN = "0-333-45340-9 (paperback)", LCCN = "QA76.73.O212 B76 1989 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", price = "UK\pounds8.95", series = "Macmillan computer science series", acknowledgement = ack-nhfb, keywords = "occam2 (computer program language)", } @Article{Brown:1990:ISE, author = "Emil W. Brown and Anant Agrawal and Trevor Creary and Michael F. Klein and David Murata and Joseph Petolino", title = "Implementing {Sparc} in {ECL}", journal = j-IEEE-MICRO, volume = "10", number = "1", pages = "10--22", month = feb, year = "1990", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Compendex database; Science Citation Index database (1980--2000); ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", abstract = "Two companies successfully joined - forces to design a small, low-cost system capables of large mainframe performance.", acknowledgement = ack-nhfb, affiliation = "Sun Microsystems Inc, USA", classcodes = "B1265F (Microprocessors and microcomputers); B2570B (Bipolar integrated circuits); C5130 (Microprocessor chips); C5220 (Computer architecture)", classification = "714; 721; 722; 723", conference = "First Annual Hot Chips Symposium", corpsource = "Sun Microsyst. Inc., Mountain View, CA, USA", keywords = "B5000 Microprocessor; bipolar emitter-; bipolar integrated circuits; Cache Design; computer architecture; Computer Interfaces; Computers, Microcomputer; coprocessor interface; coupled logic; ECL; ecl Inverter; emitter-; Integer Unit Pipeline; integer unit pipeline; Integrated Circuits, VLSI; Logic Circuits, Emitter Coupled; microprocessor chips; RISC Architecture; scalable processor architecture; Scalable Processor Architecture (Sparc); signals; Sparc; system interface; Transistors, Bipolar", meetingabr = "First Annu Hot Chips Symp", meetingaddress = "Palo Alto, CA, USA", meetingdate = "Jun 26--27 1989", meetingdate2 = "06/26--27/89", sponsor = "IEEE Computer Soc, Palo Alto, CA, USA", treatment = "P Practical", xxauthor = "E. W. Brown and A. Agrawal and T. Creary and M. F. Klein and D. Murata and J. Petolino", } @TechReport{Broy:1995:FSA, author = "M. Broy", title = "A functional specification of the {Alpha AXP} shared memory model", type = "SRC research report", number = "136", institution = "Digital Systems Research Center", address = "Palo Alto, CA, USA", pages = "34", day = "3", month = apr, year = "1995", LCCN = "TK7895.M4 B76 1994", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "computer storage devices; computer architecture; reduced instruction set computers", } @Book{Bruss:1991:RMF, author = "Rolf-Jurgen Bruss", title = "{RISC}: the {MIPS-R3000} family", publisher = pub-SIEMENS, address = pub-SIEMENS:adr, pages = "360", year = "1991", LCCN = "QA76.5.R49 1991", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "risc microprocessors; microcomputer workstations; computer architecture", } @Book{Bunda:1995:PMD, author = "John Bunda and Terence Potter and Robert Shadowen", title = "{PowerPC} microprocessor developer's guide", publisher = pub-SAMS, address = pub-SAMS:adr, pages = "xii + 400", year = "1995", ISBN = "0-672-30543-7", LCCN = "QA76.8.P67 B86 1995", bibdate = "Fri Jan 5 07:23:44 MST 2001", bibsource = "University of California MELVYL catalog", price = "US\$35.00, CDN\$47.95", series = "Sams developer's guide", acknowledgement = ack-nhfb, keywords = "PowerPC microprocessors --- programming", } @Book{Carling:1988:PPO, author = "Alison Carling", title = "Parallel processing: Occam and the transputer", publisher = "Sigma", address = "Wilmslow, Cheshire, UK", pages = "156", year = "1988", ISBN = "1-85058-077-4 (paperback)", LCCN = "QA76.6 .C375 1988 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", price = "UK\pounds12.95", acknowledgement = ack-nhfb, keywords = "parallel processing (electronic computers); occam (computer program language)", } @Book{Catanzaro:1991:STP, editor = "Ben J. Catanzaro", title = "The {SPARC} Technical Papers", publisher = pub-SV, address = pub-SV:adr, pages = "xvi + 501", year = "1991", ISBN = "0-387-97634-5, 3-540-97634-5", LCCN = "QA76.9.A73 S65 1991", bibdate = "Wed Feb 9 01:57:02 1994", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/fparith.bib", series = "Sun technical reference library", acknowledgement = ack-nhfb, } @Book{Catanzaro:1994:MSA, author = "Ben J. Catanzaro", title = "Multiprocessor system architectures: a technical survey of multiprocessor\slash multithreaded systems using {SPARC}, multilevel bus architectures and {Solaris} {(SunOS)}", publisher = pub-PHPTR, address = pub-PHPTR:adr, pages = "xxxii + 493", year = "1994", ISBN = "0-13-089137-1", LCCN = "QA76.5.C3864 1994", bibdate = "Fri Aug 7 08:29:38 MDT 1998", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/multithreading.bib", acknowledgement = ack-nhfb, keywords = "computer architecture; multiprocessors; Sun computers", } @Article{Cates:1988:PAC, author = "Ron Cates", title = "Processor architecture considerations for embedded controller applications", journal = j-IEEE-MICRO, volume = "8", number = "3", pages = "28--38", month = jun, year = "1988", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Compendex database; Science Citation Index database (1980--2000); ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", acknowledgement = ack-nhfb, affiliationaddress = "VLSI Technology Inc, Tempe, AZ, USA", classcodes = "C5130 (Microprocessor chips); C5220 (Computer architecture)", classification = "722; 723; 731", corpsource = "VLSI Technol. Inc., Tempe, AZ, USA", keywords = "32 bit; 32-bit VL86C010; Acorn RISC; Applications; computer architecture; computer networks --- Control; computers, microcomputer; control systems, digital --- Computer Interfaces; direct memory access controller (DMAC); embedded controller; embedded controller applications; general-purpose cpu; general-purpose CPU; latency; microprocessor chips; network interface; processor architecture; reduced instruction set computing; reduced-instruction-set computer; reduced-instruction-set computer (RISC); system; system latency impact", treatment = "P Practical", } @Book{Chakravarty:1994:PCA, author = "Dipto Chakravarty and Casey Cannon", title = "{PowerPC} --- concepts, architecture, and design", publisher = pub-MCGRAW-HILL, address = pub-MCGRAW-HILL:adr, pages = "xx + 362", year = "1994", ISBN = "0-07-11192-8 (invalid checksum??)", LCCN = "QA76.8.P67 C48 1994", bibdate = "Fri Jan 5 07:23:44 MST 2001", bibsource = "University of California MELVYL catalog", price = "US\$34.95", series = "J. Ranade workstation series", acknowledgement = ack-nhfb, keywords = "PowerPC microprocessors", } @Article{Check:1999:CGG, author = "M. A. Check and T. J. Slegel", title = "Custom {S/390 G5} and {G6} microprocessors", journal = j-IBM-JRD, volume = "43", number = "5/6", pages = "671--680", month = "????", year = "1999", CODEN = "IBMJAE", ISSN = "0018-8646", bibdate = "Wed Apr 19 18:58:23 MDT 2000", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ibmjrd.bib", URL = "http://www.research.ibm.com/journal/rd/435/check.html", acknowledgement = ack-nhfb, } @Book{Chow:1989:MXR, author = "Paul Chow", title = "The {MIPS-X RISC} microprocessor", publisher = pub-KLUWER, address = pub-KLUWER:adr, pages = "xxiv + 231", year = "1989", ISBN = "0-7923-9045-8", LCCN = "QA76.8.M524 M57 1989", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", series = "The Kluwer international series in engineering and computer science", acknowledgement = ack-nhfb, keywords = "MIPS-X (microprocessor); VLSI, computer architecture, and digital signal processing SECS 81", } @Article{Cmelik:1991:AMS, author = "Robert F. Cmelik and Shing I. Kong and David R. Ditzel and Edmund J. Kelly", title = "An Analysis of {MIPS} and {SPARC} Instruction Set Utilization on the {SPEC} Benchmarks", journal = j-SIGPLAN, volume = "26", number = "4", pages = "290--301 (or 290--302??)", month = apr, year = "1991", CODEN = "SINODQ", ISSN = "0362-1340", bibdate = "Tue Dec 12 09:20:21 MST 1995", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/fparith.bib", abstract = "The dynamic instruction counts of MIPS and SPARC are compared using the SPEC benchmarks. MIPS typically executes more user-level instructions than SPARC. This difference can be accounted for by architectural differences, compiler differences, and library differences. The most significant differences are that SPARC's double-precision floating point load/store is an architectural advantage in the SPEC floating point benchmarks while MIPS's compare-and-branch instruction is an architectural advantage in the SPEC integer benchmarks. After the differences in the two architectures are isolated, it appears that although MIPS and SPARC each have strengths and weaknesses in their compilers and library routines, the combined effect of compilers and library routines does not give either MIPS or SPARC a clear advantage in these areas.", acknowledgement = ack-nhfb, affiliation = "Sun Microsyst. Inc., Mountain View, CA, USA", classification = "C5220 (Computer architecture); C5470 (Performance evaluation and testing); C6140B (Machine-oriented languages)", confdate = "8-11 April 1991", conflocation = "Santa Clara, CA, USA", confsponsor = "IEEE; ACM", keywords = "Architectural differences; Compare-and-branch instruction; Compiler differences; Double-precision floating point load/store; Dynamic instruction counts; Instruction set utilization; Library differences; MIPS; SPARC; SPEC floating point benchmarks; SPEC integer benchmarks; User-level instructions", thesaurus = "Instruction sets; Performance evaluation; Reduced instruction set computing", } @Book{Cockcroft:1998:SPT, author = "Adrian Cockcroft", title = "{Sun} Performance and Tuning: {SPARC} and {Solaris}", publisher = pub-PHPTR, address = pub-PHPTR:adr, edition = "Second", pages = "xxxvi + 587", year = "1998", ISBN = "0-13-095249-4", LCCN = "QA76.8.S86C63 1998", bibdate = "Fri Jan 22 09:54:46 1999", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/unix.bib", URL = "http://www.fdds.com/books/catalog/books_comingsoon.html", acknowledgement = ack-nhfb, } @Book{Cok:1991:PPT, author = "Ronald S. Cok", title = "Parallel programs for the transputer", publisher = pub-PH, address = pub-PH:adr, pages = "xii + 242", year = "1991", ISBN = "0-13-651480-4 (paperback)", LCCN = "QA76.6 .C6245 1991 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "transputers --- programming; parallel programming (computer science)", } @Book{Dandamudi:1998:IAL, author = "Sivarama P. Dandamudi", title = "Introduction to assembly language programming: from 8086 to {Pentium} processors", publisher = pub-SV, address = pub-SV:adr, pages = "xxii + 644", year = "1998", ISBN = "0-387-98530-1", LCCN = "QA76.73.A8 D36 1998", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", series = "Undergraduate texts in computer science", acknowledgement = ack-nhfb, keywords = "assembler language (computer program language); microprocessors --- programming", } @Article{Darley:1990:TFC, author = "Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang", title = "The {TMS390C602A} Floating-Point Coprocessor for {Sparc} Systems", journal = j-IEEE-MICRO, volume = "10", number = "3", pages = "36--47", month = jun, year = "1990", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Sat Feb 24 15:01:45 MST 1996", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/fparith.bib", abstract = "A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)", acknowledgement = ack-nhfb, affiliation = "Texas Instrum. Inc., Dallas, TX, USA", classification = "B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5230 (Digital arithmetic methods)", keywords = "TMS390C602A floating-point coprocessor; Sparc systems; Two-chip configuration; TMS390C601 integer unit; TMS390C602A floating-point unit; Linpack benchmark; Addition; Subtraction; Multiplication; Division; Square root; Compare; Convert", language = "English", pubcountry = "USA", thesaurus = "Digital arithmetic; Microprocessor chips", } @Article{Darley:1990:TFP, author = "Merrick Darley and Bill Kronlage and David Bural and Bob Churchill and David Pulling and Paul Wang and Rick Iwamoto and Larry Yang", title = "The {TMS390C602A} Floating-Point Coprocessor for {Sparc} Systems", journal = j-IEEE-MICRO, volume = "10", number = "3", pages = "36--47", month = jun, year = "1990", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Compendex database; garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt; Science Citation Index database (1980--2000); ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", abstract = "A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware in the FPU increases the performance of the system. Running at clock periods as small as 20 ns, the chip should deliver 5.5 million double-precision floating-point operations per second under the Linpack benchmark (50-MHz clock rate). The FPU provides single- and double-precision arithmetic functions: addition, subtraction, multiplication, division, square root, compare, and convert. To minimize its math unit's latency, the FPU uses a highly parallel architecture requiring separate math units to optimize additions and multiplications. Traps stop the execution of a program to jump to software routine for handling data-dependent errors or to execute instructions not implemented in the hardware. Benchmark results are presented. (4 Refs.)", acknowledgement = ack-nj # " and " # ack-nhfb, affiliation = "Texas Instruments Inc, Dallas, TX, USA", classcodes = "B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5230 (Digital arithmetic methods)", classification = "B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5230 (Digital arithmetic methods); 721; 722; 723", conference = "First Annual Hot Chips Symposium", corpsource = "Texas Instrum. Inc., Dallas, TX, USA", keywords = "TMS390C602A floating-point coprocessor; Sparc systems; Two-chip configuration; TMS390C601 integer unit; TMS390C602A floating-point unit; Linpack benchmark; Addition; Subtraction; Multiplication; Division; Square root; Compare; Convert; addition; chip configuration; compare; Computer Architecture--Reduced Instruction Set Computing; Computer Systems, Digital--Parallel Processing; convert; digital arithmetic; division; Floating-Point Coprocessor; floating-point unit; Highly Parallel Architecture; Linpack benchmark; Microprocessor Chips; microprocessor chips; multiplication; Multiplier Data Path; Sparc Systems; Sparc systems; square root; subtraction; TMS390C601 integer unit; TMS390C602A; TMS390C602A floating-point coprocessor; two-", meetingabr = "First Annu Hot Chips Symp", meetingaddress = "Palo Alto, CA, USA", meetingdate = "Jun 26--27 1989", meetingdate2 = "06/26--27/89", sponsor = "IEEE Computer Soc, Palo Alto, CA, USA", thesaurus = "Digital arithmetic; Microprocessor chips", treatment = "P Practical", } @TechReport{Demshki:2000:DII, author = "Michael Demshki and Melvin Benedict and Dong Wei and Tomm Aldridge", title = "Designing Interoperability into {IA-64} Systems: {DIG64} Guidelines", type = "Technical Report", institution = pub-INTEL, address = pub-INTEL:adr, pages = "56", year = "2000", bibdate = "Fri Jan 05 10:53:56 2001", URL = "http://developer.intel.com/design/ia-64/idfdIG2/", acknowledgement = ack-nhfb, bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @Book{Dewar:1990:MPV, author = "Robert B. K. Dewar and Matthew Smosna", title = "Microprocessors: a programmer's view", publisher = pub-MCGRAW-HILL, address = pub-MCGRAW-HILL:adr, pages = "xvii + 462", year = "1990", ISBN = "0-07-016638-2, 0-07-016639-0 (soft)", LCCN = "????", bibdate = "Sat Feb 24 15:01:45 MST 1996", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/fparith.bib", acknowledgement = ack-nhfb, annote = "Includes bibliographical references. Microprocessors --- Introduction to the 80386 --- Addressing and memory on the 80386 --- Tasking, virtual memory, and exceptions to the 80386 --- Microprocessors and floating-point arithmetic --- 68030 user programming model --- 68030 supervisor state --- Introduction to RISC architectures --- MIPS processors --- SPARC architecture --- Intel i860 --- IBM RISC chips --- INMOS transputer - - Future of microprocessor design.", keywords = "Microprocessors --- Programming.", } @Article{Diefendorff:1994:EPA, author = "Keith Diefendorff and Rich Oehler and Ron Hochsprung", title = "Evolution of the {PowerPC} Architecture", journal = j-IEEE-MICRO, volume = "14", number = "2", pages = "34--49", month = apr, year = "1994", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Science Citation Index database (1980--2000); ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", abstract = "Building on the POWER architecture to support a new generation of high-performance, low-cost computers", acknowledgement = ack-nhfb, classcodes = "C5220 (Computer architecture)", corpsource = "Motorola Inc., Austin, TX, USA", keywords = "architecture; computer architecture; IBM's POWER; multiprocessor support; opcode assignments; PowerPC architecture; programming model; reduced instruction set computing; RISC architecture", treatment = "P Practical", } @Article{Diefendorff:2000:AEP, author = "Keith Diefendorff and Pradeep K. Dubey and Ron Hochsprung and Hunter Scales", title = "{AltiVec} Extension to {PowerPC} Accelerates Media Processing", journal = j-IEEE-MICRO, volume = "20", number = "2", pages = "85--95", month = mar # "\slash " # apr, year = "2000", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "http://www.computer.org/micro/mi2000/; Science Citation Index database (1980--2000)", URL = "http://dlib.computer.org/mi/books/mi2000/pdf/m2085.pdf", acknowledgement = ack-nhfb, } @Misc{Ditzel:1992:SVA, author = "David Roger Ditzel", title = "{SPARC} Version 9: adding 64-bit addressing and robustness to an existing {RISC} architecture", publisher = pub-UNIV-VIDEO-COMM, address = pub-UNIV-VIDEO-COMM:adr, year = "1992", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Video sponsored by Sun Microsystems Laboratories, Inc. Includes bibliographical references (on container for videocassette). Recorded on Sept. 18, 1992.\par From the videocassette container: ``SPARC started as a 32-bit RISC Instruction Set Architecture. This talk describes the evolution of SPARC to a full 64-bit architecture, and the design decisions that drove those changes. In addition to extending the address range, a number of changes were made to better support compilers, operating systems, superscalar implementations, context switching, and fault tolerant systems.''", series = "Leaders in computer science and electrical engineering", acknowledgement = ack-nhfb, keywords = "computer architecture", } @TechReport{Doran:1999:EFI, author = "Mark Doran", title = "{Extensible Firmware Interface}: booting the new generation of {Intel Architecture} platforms", type = "Technical report", institution = pub-INTEL, address = pub-INTEL:adr, pages = "45", day = "1", month = sep, year = "1999", bibdate = "Fri Jan 05 10:58:29 2001", URL = "http://developer.intel.com/design/ia-64/downloads/IDFEFI.htm", acknowledgement = ack-nhfb, bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @Article{Dorweiler:1997:DMC, author = "P. J. Dorweiler and F. E. Moore and D. D. Josephson and G. T. Colon-Bonet", title = "Design Methodologies and Circuit Design Trade-Offs for the {HP PA 8000} Processor", journal = j-HEWLETT-PACKARD-J, volume = "48", number = "4", pages = "16--21", month = aug, year = "1997", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Wed Mar 25 15:17:10 MST 1998", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", URL = "http://www.hp.com/hpj/97aug/au97a2.htm", abstract = "The increasing demands for greater processor performance to remain competitive in today's computer market necessitate careful attention to the methods used in designing processors to achieve these performance goals. Processor designs are increasing in complexity to meet performance goals, with such features as out-of-order execution and super-scalar operation. Design cycles are decreasing in length, so design quality must increase as well. All of these factors call for new design techniques to ensure continued success. This paper presents some of the design methodologies and choices used in the design of the HP PA 8000 CPU, the first HP processor to implement the PA-RISC 2.0 architecture and the first capable of 64-bit operation. The various design methods used in the PA 8000, specific design techniques for the new packaging technology used, the clock distribution scheme, and cross-chip signal integrity issues are discussed. We also present some of the new tools and techniques employed by HP to ensure a high level of quality on first silicon, based in large part on our experiences with previous PA-RISC microprocessor designs.", acknowledgement = ack-nhfb, classification = "B0170J (Product packaging); B1130B (Computer-aided circuit analysis and design); B1265B (Logic circuits); B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5210B (Computer-aided logic design); C7410D (Electronic engineering computing)", keywords = "circuit design trade-offs; clock distribution scheme; design methodologies; design quality; HP PA 8000 CPU; HP PA 8000 processor; logic CAD; microprocessor chips; out-of-order execution; PA-RISC 2.0 architecture; packaging; performance goals; processor performance; signal integrity issues; super-scalar operation", treatment = "A Application; P Practical", } @TechReport{Doshi:1999:UIA, author = "Gautam Doshi", title = "Understanding the {IA-64} Architecture", type = "Technical report", institution = pub-INTEL, address = pub-INTEL:adr, pages = "65", day = "31", month = aug, year = "1999", bibdate = "Fri Jan 05 09:43:01 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/idfisa/index.htm", acknowledgement = ack-nhfb, } @TechReport{Doshi:2000:IPP, author = "{Intel Corporation}", title = "{Itanium} Processor Program Update", type = "Technical report", institution = pub-INTEL, address = pub-INTEL:adr, year = "2000", bibdate = "Fri Jan 05 09:45:51 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/IDFprogram_progress/", acknowledgement = ack-nhfb, } @InProceedings{Dubey:1997:ATA, author = "Pradeep Dubey", title = "Afternoon Tutorial: Architectural and Design Implications of Mediaprocessing", crossref = "IEEE:1997:HCI", pages = "??--??", year = "1997", bibdate = "Mon Jan 08 16:33:30 2001", bibsource = "ftp://www.hotchips.org/pub/hotc7to11cd/hc97/pdf_images/hc97nav.txt", acknowledgement = ack-nhfb, } @TechReport{Dubey:1998:ADI, author = "Pradeep Dubey", title = "Architectural and Design Implications of Mediaprocessing", type = "Technical Report", institution = pub-IBM, address = pub-IBM:adr, day = "20", month = may, year = "1998", bibdate = "Tue Jan 09 14:22:55 2001", URL = "http://www.research.ibm.com/people/p/pradeep/media_tutorial/", acknowledgement = ack-nhfb, } @Article{Dulong:1998:IAW, author = "Carole Dulong", title = "The {IA-64} Architecture at Work", journal = j-COMPUTER, volume = "31", number = "7", pages = "24--32", month = jul, year = "1998", CODEN = "CPTRB4", ISSN = "0018-9162", bibdate = "Tue Jul 7 07:46:32 MDT 1998", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/computer1990.bib", URL = "http://www.computer.org/computer/co1998/r7024abs.htm; http://dlib.computer.org/co/books/co1998/pdf/r7024.pdf", acknowledgement = ack-nhfb, } @Book{Edwards:1991:OTC, author = "Janet Edwards", title = "Occam and the transputer, current developments", publisher = pub-IOS, address = pub-IOS:adr, pages = "viii + 247", year = "1991", ISBN = "90-5199-063-4", ISSN = "0925-4986", LCCN = "QA76.73.O2 W67 1991 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", price = "UK\pounds47.00", series = "Transputer and occam engineering series", acknowledgement = ack-nhfb, keywords = "occam (computer program language) congresses; transputers --- congresses", } @Book{Ellison:1990:UOT, author = "D. Ellison", title = "Understanding {Occam} and the transputer: through complete, working programs", publisher = "Sigma", address = "London, UK", pages = "v + 204", year = "1990", ISBN = "1-85058-206-8 (paperback)", LCCN = "QA76.73.O3E54 1990", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "occam (computer program language)", } @Book{Engel:1999:PJV, author = "Joshua Engel", title = "Programming for the {Java} Virtual Machine", publisher = pub-AW, address = pub-AW:adr, pages = "352", year = "1999", ISBN = "0-201-30972-6", LCCN = "QA76.73.J38E543 1999", bibdate = "Tue May 11 08:13:32 1999", price = "US\$39.95", acknowledgement = ack-nhfb, } @Book{Evans:1999:ARA, author = "James S. Evans and Richard H. Eckhouse", title = "{Alpha RISC} architecture for programmers", publisher = pub-PHPTR, address = pub-PHPTR:adr, pages = "xviii + 426", year = "1999", ISBN = "0-13-081438-5", LCCN = "QA 76.8 A176 E93 1999", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Alpha (microprocessor); RISC microprocessors; assembler language (computer program language); computer architecture", } @Book{Farquhar:1994:MPH, author = "Erin Farquhar and Philip Bunce", title = "The {MIPS} programmer's handbook", publisher = pub-MORGAN-KAUFMANN, address = pub-MORGAN-KAUFMANN:adr, pages = "viii + 408", year = "1994", ISBN = "1-55860-297-6", LCCN = "QA76.6 .F375 1994", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "embedded computer systems --- programming; MIPS1 (microprocessor)", } @Book{Fleming:1988:PPC, author = "P. J. Fleming", title = "Parallel processing in control: the transputer and other architectures", volume = "38", publisher = pub-PEREGRINUS, address = pub-PEREGRINUS:adr, pages = "xiv + 243", year = "1988", ISBN = "0-86341-136-3", LCCN = "TJ223.M53 P37 1988", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", series = "IEE control engineering series", acknowledgement = ack-nhfb, keywords = "digital control systems; parallel processing (electronic computers)", } @Article{Fong:1997:SII, author = "J. C. Fong and Hoi-Kuen Chan and M. D. Kruckenberg", title = "Solving {IC} Interconnect Routing for an Advanced {PA-RISC} Processor", journal = j-HEWLETT-PACKARD-J, volume = "48", number = "4", pages = "40--45", month = aug, year = "1997", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Wed Mar 25 15:17:10 MST 1998", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", URL = "http://www.hp.com/hpj/97aug/au97a5.htm; http://www.hp.com/hpj/97aug/tc-08-97.htm", abstract = "This paper discusses some important new block routing technologies that were required for the HP PA 8000 processor chip. These technologies are implemented in a new block routing system called PA Route.", acknowledgement = ack-nhfb, classification = "B1130B (Computer-aided circuit analysis and design); B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C7410D (Electronic engineering computing)", keywords = "advanced PA-RISC processor; block routing technologies; circuit layout CAD; Hewlett Packard computers; HP PA 8000 processor chip; IC interconnect routing; microprocessor chips; PA Route", treatment = "P Practical", } @Article{Frink:1992:HDL, author = "Craig R. Frink and Robert J. Hammond and John A. Dykstal and Don C. {Soltis, Jr.}", title = "High-performance designs for the low-cost {PA-RISC} desktop", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "4", pages = "55--63", month = aug, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Tue Mar 25 14:12:15 MST 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", abstract = "The paper presents the processor, memory, graphics, multimedia, and built-in core I/O design of the new HP 9000 Models 705 and 710 entry-level, scalable, PA-RISC workstations. The use of a buffered CPU/memory interconnect is important for scaling the high-frequency, high-performance processor design to the entry-level desktop.", acknowledgement = ack-nhfb, affiliation = "Hewlett Packard Co., Palo Alto, CA, USA", classcodes = "C5430 (Microcomputers)", classification = "C5430 (Microcomputers)", corpsource = "Hewlett Packard Co., Palo Alto, CA, USA", keywords = "Buffered CPU/memory interconnect; buffered CPU/memory interconnect; Built-in core I/O design; built-in core I/O design; computer evaluation; desktop; entry-level; Entry-level desktop; Graphics; graphics; Hewlett Packard computers; HP 9000 Model 710; HP 9000 Models 705; instruction set computing; Memory; memory; Multimedia; multimedia; PA-RISC; PA-RISC workstations; Processor; processor; reduced; workstations", thesaurus = "Computer evaluation; Hewlett Packard computers; Reduced instruction set computing; Workstations", treatment = "P Practical; R Product Review", } @TechReport{Fuller:1998:MAT, author = "Sam Fuller", title = "{Motorola}'s {AltiVec} Technology", type = "Technical Report", number = "ALTIVECWP/D", institution = pub-MOTOROLA, address = pub-MOTOROLA:adr, pages = "4", year = "1998", bibdate = "Tue Jan 09 11:25:58 2001", URL = "http://a1888.g.akamai.net/7/1888/787/83ade987b85512/www.motorola.com/SPS/PowerPC/teksupport/teklibrary/papers/altivec_wp.pdf", acknowledgement = ack-nhfb, } @Book{Furber:2000:ASC, author = "Steve Furber", title = "{ARM} System-on-Chip Architecture", publisher = pub-AW-LONGMAN, address = pub-AW-LONGMAN:adr, edition = "Second", pages = "xii + 449", year = "2000", ISBN = "0-201-67519-6", LCCN = "QA76.5 .F8643 2000", bibdate = "Tue Jan 09 13:20:08 2001", note = "Also available in Japanese translation, {\em ARM Processor}, C Q Publishing Co., Ltd. ISBN 4-7898-3351-8.", price = "US\$39.95", acknowledgement = ack-nhfb, } @Article{Gleason:1992:VCL, author = "Craig A. Gleason and Leith Johnson and Steven T. Mangelsdorf and Thomas O. Meyer and Mark A. Forsyth", title = "{VLSI} circuits for low-end and midrange {PA-RISC} computers", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "4", pages = "12--22", month = aug, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Tue Mar 25 14:12:15 MST 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", abstract = "The major VLSI chips for the HP 9000 Series 700 workstations include a central processing unit with 577000 transistors, a floating-point coprocessor with 640000 transistors, and a memory and input/output controller with 185000 transistors.", acknowledgement = ack-nhfb, affiliation = "Hewlett Packard Co., Palo Alto., CA, USA", classcodes = "B1265F (Microprocessors and microcomputers); B1265D (Memory circuits); C5130 (Microprocessor chips); C5430 (Microcomputers); C5220 (Computer architecture); C5320G (Semiconductor storage)", classification = "B1265D (Memory circuits); B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5220 (Computer architecture); C5320G (Semiconductor storage); C5430 (Microcomputers)", corpsource = "Hewlett Packard Co., Palo Alto., CA, USA", keywords = "Central processing unit; central processing unit; computer architecture; coprocessor; floating-point; Floating-point coprocessor; Hewlett Packard computers; HP 9000 Series 700; HP 9000 Series 700 workstations; Input/output controller; input/output controller; integrated; Memory; memory; memory circuits; microprocessor chips; PA-RISC computers; VLSI; VLSI circuits; workstations", thesaurus = "Computer architecture; Hewlett Packard computers; Integrated memory circuits; Microprocessor chips; VLSI; Workstations", treatment = "P Practical", } @Book{Goldenberg:1994:OAI, author = "Ruth E. Goldenberg and Saro Saravanan", title = "{OpenVMS AXP} internals and data structures: version 1.5", publisher = pub-DP, address = pub-DP:adr, pages = "xxvi + 1672", year = "1994", ISBN = "1-55558-120-X", LCCN = "QA76.76.O63 G6378 1994", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "openvms; operating systems (computers)", } @Book{Goodman:1993:PVC, author = "James (James L.) Goodman and Karen Miller", title = "A programmer's view of computer architecture: with Assembly Language examples from the {MIPS RISC} architecture", publisher = pub-SAUNDERS, address = pub-SAUNDERS:adr, pages = "xi + 402", year = "1993", ISBN = "0-03-097219-1", LCCN = "QA76.9.A73 G63 1993", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "computer architecture; Reduced Instruction Set Computers (RISC)", } @Book{Graham:1990:TH, author = "Ian Graham and Tim King", title = "The transputer handbook", publisher = pub-PHI, address = pub-PHI:adr, pages = "xi + 200", year = "1990", ISBN = "0-13-929134-2", LCCN = "TK7895.T73 G73 1990", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "transputers", } @InProceedings{Greenley:1995:UNG, author = "D. Greenley and others", title = "{UltraSPARC}: the next generation superscalar 64-bit {SPARC}", crossref = "IEEE:1995:DPC", pages = "442--451", month = mar, year = "1995", bibdate = "Thu Apr 2 08:38:35 1998", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/fparith.bib", acknowledgement = ack-sfo # " and " # ack-nhfb, } @Article{Grimes:1989:IIP, author = "Jack D. Grimes and Les Kohn and Rajeev Bharadhwaj", title = "The {Intel i860} 64-Bit Processor: a General-Purpose {CPU} with {3D} Graphics Capabilities", journal = j-IEEE-CGA, volume = "9", number = "4", pages = "85--94", month = jul, year = "1989", CODEN = "ICGADZ", ISSN = "0272-1716", bibdate = "Sat Jan 25 06:42:48 MST 1997", bibsource = "Graphics/siggraph/89.bib, Compendex database; ftp://ftp.math.utah.edu/pub/tex/bib/ieeecga.bib", acknowledgement = ack-nhfb, affiliation = "Intel Corp, Santa Clara, CA, USA", annote = "This chip and others like it are changing the shape of the computer industry. General purpose CPU optimized for graphics, with multiple processing units on board. Yesterday's supercomputer on a chip.", classification = "722; 723", journalabr = "IEEE Comput Graphics Appl", keywords = "3D Graphics Rendering Instructions; 3D Graphics Workstations; Computer Graphics; Computer Systems, Digital --- Parallel Processing; Computers, Personal; Data Processing --- Natural Sciences Applications; Fine Grained Parallelism; Interactive Scientific Visualization; parallel processing; Three Dimensional Graphics", } @Article{Halfhill:1998:II, author = "Tom R. Halfhill", title = "Inside {IA-64}", journal = j-BYTE, volume = "23", number = "6", pages = "81--??", month = jun, year = "1998", CODEN = "BYTEDJ", ISSN = "0360-5280", bibdate = "Thu Dec 10 19:10:07 1998", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/byte1995.bib", abstract = "Behind Intel\slash HP's chip for tomorrow are ideas from yesterday, like long instruction words and parallel processing.", acknowledgement = ack-nhfb, } @Article{Hangal:1999:PAV, author = "Sudheendra Hangal and Mike O'Connor", title = "Performance Analysis and Validation of the {picoJava} Processor", journal = j-IEEE-MICRO, volume = "19", number = "3", pages = "66--71", month = may # "\slash " # jun, year = "1999", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Science Citation Index database (1980--2000); http://www.computer.org/micro/mi1999/; ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", URL = "http://www.computer.org/micro/mi1999/m3066abs.htm; http://dlib.computer.org/mi/books/mi1999/pdf/m3066.pdf", acknowledgement = ack-nhfb, xxpages = "66--72", } @Article{Hansen:1992:NOP, author = "R. C. Hansen", title = "New optimizations for {PA-RISC} compilers", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "3", pages = "15--23", month = jun, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Tue Mar 25 14:12:15 MST 1997", bibsource = "Compiler/Compiler.Lins.bib; ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", abstract = "The first release of the PA-RISC 1.1 architecture is found in the HP 9000 Series 700 workstations running HP-UX 8.05. This article presents a brief discussion about the architecture extensions, followed by an overview of the enhancements made to the compilers to exploit these extensions. In addition to enhancements made to the compilers to support architecture extensions, there were a number of enhancements to traditional optimizations performed by the compilers that improve application performance, independent of the underlying architecture. These generic enhancements are also covered. Finally, performance data and an analysis are presented.", acknowledgement = ack-nhfb, affiliation = "Hewlett-Packard Co., Palo Alto, CA, USA", classcodes = "C6150C (Compilers, interpreters and other processors); C6140D (High level languages); C5220 (Computer architecture)", classification = "C5220 (Computer architecture); C6140D (High level languages); C6150C (Compilers, interpreters and other processors)", corpsource = "Hewlett-Packard Co., Palo Alto, CA, USA", keywords = "700 workstations; Architecture extensions; architecture extensions; computing; evaluation; Hewlett Packard computers; HP 9000 Series; HP 9000 Series 700 workstations; HP-UX 8.05; optimisation; PA-RISC 1.1 architecture; PA-RISC compilers; performance; Performance data; performance data; program compilers; reduced instruction set", thesaurus = "Hewlett Packard computers; Optimisation; Performance evaluation; Program compilers; Reduced instruction set computing", treatment = "P Practical", } @Book{Harp:1989:TA, author = "Gordon Harp", title = "Transputer applications", publisher = pub-PITMAN, address = pub-PITMAN:adr, pages = "x + 273", year = "1989", ISBN = "0-273-02852-9 (paperback)", LCCN = "QA76.6 .T722 1989 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "parallel processing (electronic computers)", } @Book{Heath:1994:PPC, author = "Steve Heath", title = "{PowerPC}: a practical companion", publisher = pub-BUTTERWORTH-HEINEMANN, address = pub-BUTTERWORTH-HEINEMANN:adr, pages = "x + 388", year = "1994", ISBN = "0-7506-1801-9 (paperback)", LCCN = "QA76.8.P67 H68 1994", bibdate = "Fri Jan 5 07:23:44 MST 2001", bibsource = "University of California MELVYL catalog", acknowledgement = ack-nhfb, keywords = "microprocessors design", } @Book{Heinrich:1994:MRM, author = "Joe Heinrich", title = "{MIPS R4000} Microprocessor User's Manual", publisher = "MIPS Technologies, Inc.", address = "2011 N. Shoreline Blvd., Mountain View, CA 94039-7311", edition = "Second", pages = "xxx + 724", year = "1994", ISBN = "????", LCCN = "????", bibdate = "Sat Jan 06 09:09:01 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://www.mips.com/Documentation/R4400_Uman_book_Ed2.pdf", acknowledgement = ack-nhfb, } @Book{Hennessy:1990:CAQ, author = "John L. Hennessy and David A. Patterson", title = "Computer Architecture\emdash {A} Quantitative Approach", publisher = pub-MORGAN-KAUFMANN, address = pub-MORGAN-KAUFMANN:adr, pages = "xxviii + 594", year = "1990", ISBN = "1-55860-069-8", LCCN = "QA76.9.A73 P377 1990", bibdate = "Mon Jan 31 08:47:46 1994", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @Book{Hennessy:1994:COD, author = "John L. Hennessy and David A. Patterson", title = "Computer Organization and Design\emdash The Hardware\slash Software Interface", publisher = pub-MORGAN-KAUFMANN, address = pub-MORGAN-KAUFMANN:adrnew, pages = "xxiv + 648", year = "1994", ISBN = "1-55860-281-X", LCCN = "QA76.9 .C643 P37 1994", bibdate = "Wed Feb 2 00:08:32 1994", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", price = "US\$74.75", acknowledgement = ack-nhfb, } @Book{Hennessy:1996:CAQ, author = "John L. Hennessy and David A. Patterson", title = "Computer Architecture\emdash {A} Quantitative Approach", publisher = pub-MORGAN-KAUFMANN, address = pub-MORGAN-KAUFMANN:adr, edition = "Second", pages = "xxiii + 760 + A-77 + B-47 + C-26 + D-26 + E-13 + R-16 + I-14", year = "1996", ISBN = "1-55860-329-8", LCCN = "QA76.9.A73P377 1995", bibdate = "Mon May 20 10:01:59 2002", price = "US\$69.95", } @Book{Hennessy:1997:COH, author = "John L. Hennessy and David A. Patterson", title = "Computer Organization: The Hardware\slash Software Interface", publisher = pub-MORGAN-KAUFMANN, address = pub-MORGAN-KAUFMANN:adrnew, edition = "Second", pages = "1000", year = "1997", ISBN = "1-55860-428-6 (hardcover), 1-55860-491-X (softcover)", LCCN = "QA76.9.C643H46 1997", bibdate = "Thu Sep 11 07:05:47 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", price = "US\$78.95", acknowledgement = ack-nhfb, } @Book{Hennessy:2002:CAQ, author = "John L. Hennessy and David A. Patterson", title = "Computer Architecture\emdash {A} Quantitative Approach", publisher = pub-MORGAN-KAUFMANN, address = pub-MORGAN-KAUFMANN:adr, edition = "Third", pages = "xxi + 883 + A-87 + B-42 + C-1 + D-1 + E-1 + F-1 + G-1 + H-1 + I-1 + R-22 + I-44", year = "2002", ISBN = "1-55860-596-7", LCCN = "????", bibdate = "Fri May 31 15:46:29 2002", price = "US\$89.95", URL = "http://www.mkp.com/CA3; http://www.mkp.com/books_catalog/catalog.asp?ISBN=1-55860-596-7", } @Book{Hinton:1993:THS, author = "Jeremy Hinton and Alan Pinder", title = "Transputer hardware and system design", publisher = pub-PH, address = pub-PH:adr, pages = "x + 286", year = "1993", ISBN = "0-13-953001-0", LCCN = "TK7895.T73 H56 1993 Bar", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "transputers; system design", } @Book{Holt:1988:BRE, author = "Wayne E. Holt and Steven M. Cooper", title = "Beyond {RISC}: an essential guide to {Hewlet-Packard} precision architecture", publisher = "Software Research Northwest", address = "Vashon Island, WA", pages = "xvii + 342", year = "1988", ISBN = "0-9618813-7-2", LCCN = "QA 76.8 H66 B49 1988", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "HP 3000 (computer); Hewlett-Packard computers", } @Article{Homewood:1987:ITT, author = "Mark Homewood and David May and David Shepherd and Roger Shepherd", title = "The {IMS} {T800} transputer", journal = j-IEEE-MICRO, volume = "7", number = "5", pages = "10--26", month = oct, year = "1987", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Parallel/transputer.bib; garbo.uwasa.fi:/pc/doc-soft/fpbiblio.txt; Compendex database; Science Citation Index database (1980--2000)", acknowledgement = ack-nj # " and " # ack-nhfb, affiliationaddress = "Inmos Ltd, Bristol, Engl", classcodes = "B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips)", classification = "714; 722; 723; 921", corpsource = "Inmos Ltd., Bristol, UK", keywords = "architecture; capability; communication links; computer architecture; computer graphics; computer programming languages; computers, microcomputer; Design; floating-point arithmetic; floating-point unit design; graphics; IMS T800 transputer; integrated circuits, VLSI; microprocessor chips; performance; scientific computer; supercomputers; telecommunication links", treatment = "P Practical; R Product Review", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", } @Manual{HP:1994:PRAa, title = "{PA-RISC 1.1} Architecture and Instruction Set Reference Manual", organization = pub-HP, edition = "Third", pages = "424", month = feb, year = "1994", bibdate = "Tue Jan 09 11:56:43 2001", note = "HP Part Number: 09740-90039. Previous editions November 1990 and September 1992.", URL = "http://devresource.hp.com/devresource/Docs/Refs/PA1_1; http://devresource.hp.com/devresource/Docs/Refs/PA1_1/pdf.html; http://devresource.hp.com/devresource/Docs/Refs/PA1_1/acd.pdf", abstract = pub-HP:adr, acknowledgement = ack-nhfb, } @Misc{HP:1994:PRAb, author = "{Hewlett-Packard Corporation}", title = "{PA-RISC 2.0} Architecture Reference", howpublished = "World-Wide Web document.", year = "1994", bibdate = "Tue Jan 09 11:56:43 2001", note = "See \cite{Kane:1996:PRA} for a printed version.", URL = "http://devresource.hp.com/devresource/Docs/Refs/PA2_0/", acknowledgement = ack-nhfb, } @Manual{HP:2000:IAD, title = "{IA-64} Architecture Disclosures", organization = pub-HP, address = pub-HP:adr, pages = "??", year = "2000", bibdate = "Tue Jan 09 12:53:32 2001", URL = "http://www.ia64.hp.com/infolibrary/whitepapers/ia64_arch_wp.pdf", acknowledgement = ack-nhfb, } @Manual{HP:2000:OIA, title = "Overview of {IA-64} Architecture", organization = pub-HP, address = pub-HP:adr, pages = "10", year = "2000", bibdate = "Tue Jan 09 12:53:32 2001", note = "This document is part of the HP-UX 11.x Software Transition Kit.", URL = "http://devresource.hp.com/STK/partner/ia64bkgnd.pdf", acknowledgement = ack-nhfb, } @Book{Hsu:2001:CAS, author = "John Y. Hsu", title = "Computer Architecture: Software Aspects, Coding, Hardware", publisher = pub-CRC, address = pub-CRC:adr, pages = "416 (est.)", year = "2001", ISBN = "0-8493-1026-1", LCCN = "A76.9.A73 H758 2001", bibdate = "Fri Jan 19 15:47:59 2001", price = "US\$89.95, UK\pounds 59.99", acknowledgement = ack-nhfb, keywords = "Compaq/DEC Alpha; floating-point arithmetic; Intel x86; Java Virtual Machine; multimedia instructions; Pentium", libnote = "Not yet in my library.", } @Article{Huck:2000:IIA, author = "Jerry Huck and Dale Morris and Jonathan Ross and Allan Knies and Hans Mulder and Rumi Zahir", title = "Introducing the {IA-64} Architecture", journal = j-IEEE-MICRO, volume = "20", number = "5", pages = "12--23", month = sep # "\slash " # oct, year = "2000", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Tue Oct 10 06:00:40 MDT 2000", bibsource = "http://www.computer.org/micro/mi2000/; ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", URL = "http://www.computer.org/micro/mi2000/m5012abs.htm ; http://dlib.computer.org/mi/books/mi2000/pdf/m5012.pdf", acknowledgement = ack-nhfb, } @Book{Hull:1994:PPT, author = "M. E. C. Hull and Danny Crookes and P. J. Sweeney", title = "Parallel processing: the transputer and its applications", publisher = pub-AW, address = pub-AW:adr, pages = "xii + 328", year = "1994", ISBN = "0-201-62755-8", LCCN = "QA76.58 .P3783 1994", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", series = "International computer science series", acknowledgement = ack-nhfb, keywords = "parallel processing (electronic computers); transputers", } @Book{Inmos:1988:TIS, author = "{INMOS Limited}", title = "Transputer instruction set: a compiler writer's guide", publisher = pub-PH, address = pub-PH:adr, pages = "vii + 167", year = "1988", ISBN = "0-13-929100-8", LCCN = "QA76.76.C65 T73 1988 Sci-Eng", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Includes indexes.", acknowledgement = ack-nhfb, keywords = "compiling (electronic computers); transputers -- programming", } @Book{Inmos:1988:TRM, author = "{INMOS Limited}", title = "Transputer reference manual", publisher = pub-PH, address = pub-PH:adr, pages = "xviii + 346", year = "1988", ISBN = "0-13-929001-X", LCCN = "TK7895.T73 T73 1988 Annex", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Includes index. Bibliography: p. 315-324.", acknowledgement = ack-nhfb, keywords = "transputers; occam (computer program language)", } @Book{Inmos:1989:TD, author = "{INMOS Limited}", title = "Transputer databook", publisher = "INMOS Limited", address = "Colorado Springs, CO, USA", edition = "Second", pages = "xxii + 582", year = "1989", LCCN = "TK7895.T73 I55 1989 Sci-Eng", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "transputers --- handbooks, manuals, etc", } @Book{Inmos:1990:TDS, author = "{INMOS Limited}", title = "Transputer development system", publisher = pub-PH, address = pub-PH:adr, edition = "Second", pages = "xv + 465", year = "1990", ISBN = "0-13-929068-0", LCCN = "TK 7895 T73 T69 1990", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "INMOS document number: 72 TRN 011 01.", acknowledgement = ack-nhfb, keywords = "transputers; occam (computer program language)", } @Book{Intel:1990:IBM, author = "Intel", title = "i860 64-bit Microprocessor Hardware Reference Manual", publisher = pub-INTEL, address = pub-INTEL:adr, year = "1990", ISBN = "1-55512-106-3", LCCN = "TK7895.M5 I57662 1990", bibdate = "Wed Dec 15 10:35:21 1993", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @Book{Intel:1991:IBM, author = "Intel", title = "i860 64-bit Microprocessor Family Programmer's Reference Manual", publisher = pub-INTEL, address = pub-INTEL:adr, year = "1991", ISBN = "1-55512-135-7", LCCN = "QA76.8.I57 I44 1991", bibdate = "Wed Dec 15 10:35:26 1993", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @Book{Intel:1991:IKK, author = "{Intel Corporation}", title = "{i960 KA\slash KB} microprocessor programmer's reference manual", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1991", ISBN = "1-55512-137-3", LCCN = "QA76.8.I2932 I29 1991", bibdate = "Fri Jan 5 08:00:52 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Intel i960 (microprocessor) --- programming; computer programming --- handbooks, manuals, etc", } @Book{Intel:1991:IMM, author = "{Intel Corporation}", title = "{i960 MC} microprocessor reference manual", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1991", ISBN = "1-55512-136-5", LCCN = "QA76.8.I29284 I2 1991", bibdate = "Fri Jan 5 08:00:52 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Intel 80960 (microprocessor); microprocessors -- programming; computer programming", } @Manual{Intel:1991:OIX, title = "Overview of the {i860 XP} supercomputing microprocessor", organization = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1991", bibdate = "Fri Aug 30 08:01:51 MDT 1996", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/super.bib", acknowledgement = ack-nhfb, keywords = "Intel i860 (Microprocessor)", } @Book{Intel:1992:IXM, author = "{Intel Corporation}", title = "{i860 XP} microprocessor hardware reference manual, 1992", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1992", ISBN = "1-55512-166-7", LCCN = "QA76.6.I39 1992", bibdate = "Fri Jan 5 08:00:52 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "Intel i860 (microprocessor)", } @Book{Intel:1993:III, author = "{Intel Corporation}", title = "{i750}, {i860}, {i960} processors and related products", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1993", ISBN = "1-55512-185-3", LCCN = "TK7895.M5 I57667 1993", bibdate = "Fri Jan 5 08:00:52 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Order number: 272084-002.", acknowledgement = ack-nhfb, keywords = "microprocessors --- catalogs", } @Book{Intel:1993:PPU, author = "{Intel Corporation}", title = "{Pentium} processor user's manual", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "", year = "1993", ISBN = "1-55512-193-4 (vol. 1), 1-55512-194-2 (vol. 2)", LCCN = "QA76.8.P46P465 1993 Library has: vol. 1-3", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Contents: vol. 1. Pentium processor data abook --- vol. 2. 82496 cache controller and 82491 cache SRAM data book --- vol. 3. Architecture and programming manual.", acknowledgement = ack-nhfb, keywords = "Pentium (microprocessor); multiprocessors; cache memory", } @Book{Intel:1994:ICC, author = "{Intel Corporation}", title = "{i960 CA\slash CF} microprocessor user's manual", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", month = mar, year = "1994", ISBN = "1-55512-224-8", LCCN = "QA76.8.I29282 I55 1994", bibdate = "Fri Jan 5 08:00:52 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Includes i960 Cx Microprocessor User's Guide Instruction Set Quick Reference (18 p.) in pocket.", acknowledgement = ack-nhfb, keywords = "Intel i960 (microprocessor) --- programming handbooks, manuals, etc; computer programming --- handbooks, manuals, etc", } @Book{Intel:1994:III, author = "{Intel Corporation}", title = "{i750}, {i860}, {i960} processors and related products", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1994", ISBN = "1-55512-217-5", LCCN = "TK7895.M5 I588 1994 Sci-Eng", bibdate = "Fri Jan 5 08:00:52 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Order number 272084-003.", acknowledgement = ack-nhfb, keywords = "microprocessors --- catalogs", } @Book{Intel:1994:PPU, author = "{Intel Corporation}", title = "{Pentium} processor user's manual", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1994", ISBN = "1-55512-222-1 (vol. 2: paperback), 1-55512-221-3 (vol. 1: paperback)", LCCN = "QA76.8.P46 P46 1994", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Order numbers 241428, 241429, and 241430. Contents: vol. 1. Pentium processor data book --- vol. 2. 82496 cache controller and 82491 cache SRAM data book -- vol. 3. Architecture and programming manual.", acknowledgement = ack-nhfb, keywords = "Pentium (microprocessor); multiprocessors; cache memory", } @Book{Intel:1995:PPF, author = "{Intel Corporation}", title = "{Pentium} processor family developer's manual", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1995", LCCN = "QA76.8.P46 P458 1995", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Contents: vol. 1. Pentium processors --- vol. 2. 82496/82497/82498 cache controller and 82491/82492/82493 cache SRAM --- vol. 3. Architecture and programming manual.", acknowledgement = ack-nhfb, keywords = "Pentium (microprocessor); multiprocessors; cache memory", } @Book{Intel:1996:PPF, author = "{Intel Corporation}", title = "{Pentium pro} family developer's manual", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "various", year = "1996", ISBN = "1-55512-259-0 (vol. 1), 1-55512-260-4 (vol. 2), 1-55512-261-2 (vol. 3)", LCCN = "QA76.8.P46 P455 1996 LIBRARY HAS vol. 2", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", note = "Three volumes: vol. 1: Specifications: order number 242690; vol. 2. Programmer's reference manual: order number 242691; vol. 3. Operating system writer's guide: order number 242692.", acknowledgement = ack-nhfb, keywords = "Pentium (microprocessor); multiprocessors; cache memory", } @TechReport{Intel:1997:PIP, author = "{Intel Corporation}", title = "{Pentium II} Processor Performance Brief", type = "Technical Report", number = "XXX-001", institution = pub-INTEL, address = pub-INTEL:adr, month = may, year = "1997", bibdate = "Fri Jan 05 09:11:07 2001", bibsource = "????", acknowledgement = ack-nhfb, } @Book{Intel:1999:IAD, author = "{Intel Corporation}", title = "{IA-64} Application Developer's Architecture Guide", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "476", month = may, year = "1999", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 08:45:35 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/ADAG.pdf", acknowledgement = ack-nhfb, } @TechReport{Intel:2000:AIC, author = "{Intel Corporation}", title = "The Advantages of {IA-64} for Cache Server Software Information for Software Developers and {IT} Managers", type = "Technical report", institution = pub-INTEL, address = pub-INTEL:adr, pages = "5", year = "2000", bibdate = "Fri Jan 05 09:38:22 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/ia-64_cache2.htm", acknowledgement = ack-nhfb, alttitle = "Cache Tech Brief for {Itanium} Processor Family Architecture", } @TechReport{Intel:2000:DIG, author = "{Intel Corporation}", title = "Developer's Interface Guide for {IA-64} Servers", type = "Technical report", institution = pub-INTEL, address = pub-INTEL:adr, year = "2000", bibdate = "Fri Jan 05 11:04:27 2001", note = "This document is a directory of pointers to white papers on the DIG-64 (Developer's Interface Guide) specifications.", URL = "http://developer.intel.com/design/servers/dev_guides/content/doc_lib/index.htm", acknowledgement = ack-nhfb, bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @Book{Intel:2000:IBL, author = "{Intel Corporation}", title = "{Itanium}-Based {Linux} Developer's Kit", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "????", year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 09:25:31 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/linux.htm", acknowledgement = ack-nhfb, } @Book{Intel:2000:IIAa, author = "{Intel Corporation}", title = "{Intel IA-64} Architecture Software Developer's Manual: Volume 1: {IA-64} Application Architecture", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "216", month = jan, year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 08:45:35 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/245317.htm", acknowledgement = ack-nhfb, } @Book{Intel:2000:IIAb, author = "{Intel Corporation}", title = "{Intel IA-64} Architecture Software Developer's Manual: Volume 2: {IA-64} System Architecture", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "536", month = jan, year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 08:45:35 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/245318.htm", acknowledgement = ack-nhfb, } @Book{Intel:2000:IIAc, author = "{Intel Corporation}", title = "{Intel IA-64} Architecture Software Developer's Manual: Volume 3: Instruction Set Reference", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "926", month = jan, year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 08:45:35 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/245319.htm", acknowledgement = ack-nhfb, } @Book{Intel:2000:IIAd, author = "{Intel Corporation}", title = "{Intel IA-64} Architecture Software Developer's Manual: Volume 4: {Itanium} Processor Programmer's Guide", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "76", month = jan, year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 08:45:35 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/245320.htm", acknowledgement = ack-nhfb, } @TechReport{Intel:2000:IIP, author = "{Intel Corporation}", title = "{Intel Itanium} Processor: High Performance On Security Algorithms ({RSA} Decryption Kernel)", institution = pub-INTEL, address = pub-INTEL:adr, pages = "8", year = "2000", bibdate = "Fri Jan 05 09:27:38 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/itaniumssl_seg_103.htm", acknowledgement = ack-nhfb, } @Book{Intel:2000:IPMa, author = "{Intel Corporation}", title = "{Itanium} Processor Microarchitecture Reference for Software Optimization", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "32", month = mar, year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 08:45:35 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/245473.htm", acknowledgement = ack-nhfb, } @Book{Intel:2000:IPMb, author = "{Intel Corporation}", title = "{Itanium} Processor Microarchitecture Reference for Software Optimization", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "34", month = aug, year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 09:23:17 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/downloads/245474.htm", acknowledgement = ack-nhfb, } @Book{Intel:2000:ISAa, author = "{Intel Corporation}", title = "{IA-64 System Abstraction Layer (SAL)} Specification", publisher = pub-INTEL, address = pub-INTEL:adr, pages = "120", month = jul, year = "2000", ISBN = "????", LCCN = "????", bibdate = "Fri Jan 05 10:50:32 2001", URL = "http://developer.intel.com/design/ia-64/downloads/24535902.htm", acknowledgement = ack-nhfb, bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", } @TechReport{Intel:2000:ISAb, author = "{Intel Corporation}", title = "The {IA-64} System Architecture: Tutorial for Hardware, {OS}, and Application Developers", type = "Technical report", institution = pub-INTEL, address = pub-INTEL:adr, year = "2000", bibdate = "Fri Jan 05 09:35:44 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", URL = "http://developer.intel.com/design/ia-64/archSysSoftware/", acknowledgement = ack-nhfb, } @Article{Jennings:1998:MCS, author = "Matthew D. Jennings and Thomas M. Conte", title = "Mobile Computing: Subword extensions for video processing on mobile systems", journal = j-IEEE-CONCURR, volume = "6", number = "3", pages = "13--16", month = jul # "\slash " # sep, year = "1998", CODEN = "IECMFX", ISSN = "1092-3063", bibdate = "Mon Jun 7 07:52:29 MDT 1999", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ieeeconcurrency.bib; http://www.computer.org/concurrency/pd1998/", URL = "http://dlib.computer.org/pd/books/pd1998/pdf/p3013.pdf", acknowledgement = ack-nhfb, keywords = "3DNow!; AltiVec; MAX-2; MIPS Digital Media Extensions (MDMX); MMX; VIS", } @Article{Jessani:1996:FPU, author = "R. M. Jessani and C. H. Olson", title = "The floating point unit of the {PowerPC} 603e microprocessor", journal = j-IBM-JRD, volume = "40", number = "5", pages = "559--566", month = sep, year = "1996", CODEN = "IBMJAE", ISSN = "0018-8646", bibdate = "Tue Mar 25 14:26:59 MST 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ibmjrd.bib", URL = "http://www.almaden.ibm.com/journal/rd40-5.html#four", abstract = "The IBM PowerPC 603e* floating-point unit (FPU) is an on-chip functional unit to support IEEE 754 standard single- and double-precision binary floating-point arithmetic operations. The design objectives are to be a low-cost, low-power, high-performance engine in a single-chip superscalar microprocessor. Using less than 15 mm$^{2}$ of the available silicon area on the chip (the size of the PowerPC 603e microprocessor is 98 mm$^{2}$) and operating at the peak clock frequency of 100 MHz, an average single-pumping multiply-add-fuse instruction has one-cycle throughput and four-cycle latency. An average double-pumping multiply-add-fuse instruction has two-cycle throughput and five-cycle latency. The estimated performance at 100 MHz is 105 against the SPECfp92** benchmark.", acknowledgement = ack-nhfb, classcodes = "B1265F (Microprocessors and microcomputers); C5130 (Microprocessor chips); C5230 (Digital arithmetic methods)", corpsource = "Somerset Design Center, Motorola Inc., Austin, TX, USA", keywords = "add-fuse instruction; design objectives; digital arithmetic; double-pumping multiply-add-fuse; floating point unit; functional unit; IEEE 754 standard; instruction; microprocessor chips; on-chip; peak clock frequency; PowerPC 603e microprocessor; silicon area; single-pumping multiply-", treatment = "A Application; P Practical", xxlibnote = "Issue missing from UofUtah Marriott Library", } @Book{Kacmarcik:1995:OPC, author = "Gary Kacmarcik", title = "Optimizing {PowerPC} code: programming the {PowerPC} chip in assembly language", publisher = pub-AW, address = pub-AW:adr, pages = "viii + 694", year = "1995", ISBN = "0-201-40839-2", LCCN = "QA76.8.P67 K33 1995", bibdate = "Fri Jan 5 07:23:44 MST 2001", bibsource = "University of California MELVYL catalog", acknowledgement = ack-nhfb, keywords = "PowerPC microprocessors", } @Article{Kahaner:1992:TD, author = "D. K. Kahaner", title = "Transputers and Databases", journal = j-IEEE-MICRO, volume = "12", number = "6", pages = "88--89", month = dec, year = "1992", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Thu Dec 14 06:08:58 MST 2000", bibsource = "Science Citation Index database (1980--2000)", acknowledgement = ack-nhfb, bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/ieeemicro.bib", } @Book{Kane:1987:MRR, author = "Gerry Kane", title = "{MIPS R2000 RISC} architecture", publisher = pub-PH, address = pub-PH:adr, pages = "various", year = "1987", ISBN = "0-13-584749-4 (paperback)", LCCN = "QA76.8.M52 K36 1988", bibdate = "Fri Jan 5 11:51:46 MST 2001", bibsource = "University of California MELVYL catalog.", acknowledgement = ack-nhfb, keywords = "MIPS R2000 series microprocessors; computer architecture; reduced instruction set computers", } @Book{Kane:1989:MRR, author = "Gerry Kane", title = "{MIPS R2000 RISC} Architecture", publisher = pub-PH, address = pub-PH:adr, pages = "various", year = "1989", ISBN = "0-13-584293-X", LCCN = "QA76.8.M52 K37 1988", bibdate = "Wed Dec 15 17:51:38 1993", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", acknowledgement = ack-nhfb, keywords = "computer architecture; MIPS R2000 series microprocessors", } @Book{Kane:1992:MRA, author = "Gerry Kane and Joe Heinrich", title = "{MIPS RISC} Architecture", publisher = pub-PH, address = pub-PH:adr, pages = "various", year = "1992", ISBN = "0-13-590472-2", LCCN = "QA76.8.M52 K37 1992", bibdate = "Wed Dec 15 10:35:45 1993", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", keywords = "MIPS R2000 series microprocessors; computer architecture; reduced instruction set computers", } @Book{Kane:1996:PRA, author = "Gerry Kane", title = "{PA-RISC 2.0} architecture", publisher = pub-PHPTR, address = pub-PHPTR:adr, pages = "various", year = "1996", ISBN = "0-13-182734-0", LCCN = "QA76.8.H48K36 1996", bibdate = "Tue Jan 09 12:34:37 2001", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/master.bib", price = "US\$34.40", acknowledgement = ack-nhfb, keywords = "Hewlett-Packard computers; PA-RISC microprocessors", URL = "http://devresource.hp.com/devresource/Docs/Refs/PA2_0/updates/index.html; http://devresource.hp.com/devresource/Docs/Refs/PA2_0/index.html", } @Article{Keltcher:2003:AOP, author = "Chetana N. Keltcher and Kevin J. McGrath and Ardsher Ahmed and Pat Conway", title = "The {AMD Opteron} Processor for Multiprocessor Servers", journal = j-IEEE-MICRO, volume = "23", number = "2", pages = "66--76", month = mar # "\slash " # apr, year = "2003", CODEN = "IEMIDZ", ISSN = "0272-1732", bibdate = "Wed Apr 23 18:57:11 MDT 2003", bibsource = "http://www.computer.org/micro/mi2003/", URL = "http://dlib.computer.org/mi/books/mi2003/pdf/m2066.pdf; http://www.computer.org/micro/mi2003/m2066abs.htm", acknowledgement = ack-nhfb, } @Article{Kerschen:1992:HOS, author = "K. Kerschen and J. R. Glasson", title = "{HP-UX} operating system kernel support for the {HP} 9000 series 700 workstations", journal = j-HEWLETT-PACKARD-J, volume = "43", number = "3", pages = "6--10", month = jun, year = "1992", CODEN = "HPJOAX", ISSN = "0018-1153", bibdate = "Tue Mar 25 14:12:15 MST 1997", bibsource = "ftp://ftp.math.utah.edu/pub/tex/bib/hpj.bib", abstract = "Summarizes the architectural enhancements of PA-RISC 1.1 and tells how the kernel of the HP-UX operating system was modified to take advantage of them. Th